In recent years tremendous technological strides have been made in the area of high capacity memory storage. Such strides are best illustrated by semiconductor memory systems utilizing field effect transistors to store information therein in the form of capacitive charges. Such memories have great potential for use in inexpensive large capacity memory systems due to their small size, low power consumption and ease of fabrication as integrated circuits. However, this type of memory suffers from the disadvantage that the capacitive storage of information is essentially volatile and, accordingly, must be periodically restored or refreshed in order to maintain the viability of the stored information. Moreover, because such memories are often formed by combining a plurality of chips into arrays to form a plurality of memory planes, numerous decoders are required to indicate the column and row of the desired chip as well as the column and row of the desired cell within the chip to which access is desired. Because of the complexity of semiconductor memories, the access circuits utilized to control access to the memories are hard to diagnose. However, to ensure the operability of a semiconductor memory system, effective diagnosis must be made of the control circuitry therein to ensure that such control circuitry is applying the proper control signals to the semiconductor memory arrays. Several prior art arrangements as discussed below have been designed to diagnose such memories.
In one prior art arrangement as disclosed in J. A. Weisbecker, U.S. Pat. No. 3,599,146, issued Aug. 19, 1971, each word stored in the semiconductor memory contained a parity bit indicating the parity over the address at which that word was stored. By first computing the actual parity over the outputs from the address register, and then by comparing that computed parity with the parity bit in the retrieved word, it could be ascertained whether the memory had been accessed at the proper address. This arrangement appears to be effective; however, the use of the memory for storage of additional diagnostic information is costly and the arrangement is limited to detecting addressing errors.
In another prior art arrangement disclosed in C. M. Nibby, U.S. Pat. No. 3,814,922, issued June 4, 1974, a maintenance status register and associated apparatus were utilized to identify and store information relating to errors arising in a semiconductor memory module. This arrangement produced error correcting code signals for stored information, which code signals were also stored in the memory module. These stored error correcting code signals were then combined with the information signals to form a group of location identifying signals. This arrangement appears to be effective but like the above-mentioned Weisbecker arrangement, the storage of diagnostic information is costly and, moreover it appears that complicated logic operations are required to detect malfunctions.
In still another prior art diagnostic arrangement, disclosed in F. V. Beck, D. C. Peterson, E. M. Prell, T. Quin, application Ser. No. 601,522, filed Aug. 4, 1975; now, U.S. Pat. No. 3,944,800, a pair of access circuits are provided with each module with each access circuit controlling the accessing of predetermined bits of each word stored in that module. During read, write, and refresh operations, the output signal generated by each of the two access circuits for application to the memory elements in that module are compared (or the parities of such output signals are compared) to ensure the memory elements are being properly accessed, and particularly that both memory halves are being accessed at the same address. This arrangement is very effective in detecting problems associated with the duplicated access circuits during memory access operations; however, it is ineffective to detect problems in nonaccessed modules. It is desirable to detect errors potentionally affecting memory operations as soon as possible, and preferably before erroneous information is given to the data processor. Taking a memory module out of service before it is accessed minimizes diagnostic problems by insuring that the past occurrence of an error condition will eventually be given to the processor. The sensitivity of access circuitry to faults affecting specific addresses makes the retention of observed error conditions crucial.
It is an object of this invention to perform diagnostic operations on nonaccessed memory modules to ensure the continued operability of the access circuits associated therewith.
It is a further object of this invention to perform such diagnostics on a noninterfering basis so that the error-free operation of the access circuits is verified without interfering with normal memory utilization.
It is a further object of this invention to diagnose the diagnostic apparatus itself during normal memory access operations without affecting such operations.